An integrated circuit (IC) package has a number of components present on a single chip to perform a specific function. Apart from the basic circuitry, each IC package has a I/O block associated with it. The function of this I/O block is to interface with other IC packages or electrical devices. A bidirectional I/O block comprises of an input buffer and an output buffer, both connected to an I/O pad. When the I/O block is used in input mode, the input buffer is in driving mode whereas the output buffer is tristated. On the other hand, when the I/O block is used in output mode, the output buffer is in driving mode whereas the input buffer is tristated.
Conventionally, IC packages utilize 0 and 5 volts voltage levels to represent “0” and “1” logic states respectively. However, with advancement in technology, these voltage levels have undergone a change. For example in many current IC devices manufactured by submicron semiconductor fabrication processes, a voltage level of 3.3 volts is used instead of 5 volts to represent logic state “1”. This reduction in the voltage level has lead to reduced power dissipation and hence improved performance of the IC devices.
With the introduction of lower voltage levels, present day IC devices work in mixed mode operation. In such a mode, circuits operating at 3.3 volts and 5 volts are coupled together. The complete logic circuit has tristate buffers operating at 3.3 volts and 5 volts. The problem associated with this type of operation is that tristate buffer operating at 3.3 volts may not be able to tolerate a 5 volts voltage level. This is explained in detail with reference to FIG. 1A, 1B and 1C. FIG. 1A shows a bidirectional I/O block. The I/O block (100) comprises of an input buffer (115) and an output buffer (120). Both the buffers are connected to a PAD (130). FIG. 1B shows a schematic of a conventional pad driver (140) of output buffer with PAD (130). In the present configuration, if the voltage at the pad (130) (VPAD) rises to (VDD+|Vtp|) where VDD is the supply voltage of the output buffer and Vtp is the threshold voltage of the PMOS, the PMOS P1 starts conducting and current starts flowing from pad to VDD. This results in power dissipation. FIG. 1C shows a detailed structure of PMOS (P1). The substrate of PMOS (P1) is connected to VDD and if the voltage at the pad increases to (VDD+Vt), where Vt is the threshold voltage of the diode D1, the diode D1 gets forward biased. This results in substrate current flow. Moreover, if the voltage across any transistor increases beyond a critical limit, the gate oxide of both PMOS and NMOS may break down. Hence it is required that |Vgs| or |Vgd| do not exceed VDD, where Vgs and Vgd are the gate to source and gate to drain voltages respectively.
In order to overcome the above mentioned problems in conventional I/O buffers, a tolerant I/O buffer is disclosed in U.S. Pat. No. 6,150,843 issued to Shiffer et al. The 5 volt tolerant I/O buffer circuit is coupled to a power supply terminal of a predetermined power supply voltage for driving an I/O pad to a logic state depending on an input signal and an output enable signal. The I/O buffer circuit minimizes current flow into the power supply terminal when the pad is coupled to a voltage greater than the predetermined power supply voltage. A driver transistor of a first type is formed within diffusion well and is coupled to the predetermined power supply voltage and to the pad. First and second terminals of a protection transistor are coupled to respective ones of the predetermined power supply voltage and the diffusion well. When the output enable signal is active, protection transistor is turned on so as to couple the predetermined power supply voltage to the diffusion well, regardless of a voltage level of the pad.
The I/O buffer in the above-described circuitry is tolerant to a voltage signal of strength 5 volts. However, the circuit faces one problem. The inverter connected to PAD dissipates power since its PMOS never becomes completely off. The circuit for 5V tolerant output buffer as disclosed by the prior art has been shown in FIG. 2. In order to make an I/O buffer 5 volt tolerant, the P driver of the I/O buffer should always be in cutoff mode when the output enable signal is inactive. As shown in FIG. 2, when the pad is at 5 volts, if the gate of the P driver P1 is at 3 volts or less, then the transistor P1 is turned on. However, this is not desired. Therefore, when the pad is at 5 volts, the gate of the transistor P1 should also be at 5 volts. This is achieved by adding a P transistor P2 as shown in FIG. 2. When the pad is at 5 volts, the transistor P2 turns on such that the gate of the transistor P1 is also at 5 volts. As a result, the transistor P1 gets into cutoff mode. A pass gate comprising of transistors N1 and P3 is provided in the circuit as shown in FIG. 2. The function of this pass gate is to isolate the 5 volt potential at the gate of the transistor P1 from predriver logic. A P transistor P4 is present between the pad and the gate of the transistor P3. Transistor P4 passes 5 volts to the gate of P3 when the pad is at 5 volts. This helps to block leakage into the predriver whenever there is 5 volts at the gate of the transistor P1. When the output enable signal is active low, the transistor P3 should pass 3 volts across the pass gate to the gate of the transistor P1. For this purpose, transistors N2 and N3 are connected in series as shown in FIG. 2. The output enable signal is input to this pair of transistors after passing through a pair of series connected inverters. The transistor N2 is always turned on since its gate is connected to VDD. The gate of the transistor N3 is connected to an intermediate node between the two inverters. As a result, the transistor N3 is turned on whenever the output enable signal is active low.
When the output enable signal is inactive, the pad may be at 0 volts. In that case, the transistor P1 should be placed in cutoff mode to prevent current leakage from VDD to the pad. For this purpose, a pair of series connected N type transistors N4 and N5 are provided in the circuit. When the pad is at 0 volts, these transistors N4 and N5 are ON and the gate of the transistor P3 is at 0 volts, this passes 3 volts to the gate of the transistor P1, turning it off. A transistor P5 is coupled between the supply voltage VDD and the N well in which each of the P transistors is formed. This transistor blocks the leakage path through the bulk. Series connected N type transistors N6 and N7 coupled from pad to ground form the N driver pull down circuitry as shown in FIG. 2.
The above mentioned circuitry provides tolerance whenever an I/O pad is driven by an external device to a voltage level higher than that to which it is driven by the I/O buffer. However, the PMOS of the inverter connected to PAD never becomes completely off. As a result, the inverter dissipates power.
In order to overcome the above mentioned problems faced by the prior art, the present invention discloses a circuit for high voltage tolerant output buffer. The circuit comprises of an input (110) coming from predriver, an output buffer (120) and a pad (130). Apart from this, the circuit is connected to a substrate voltage controlling circuit (140) and an inverter (150).
Therefore, there arises a need for an output buffer which is tolerant to high voltage and which causes less power dissipation.